74HC165D,653 OFFSET REG, 74HC165, 16 SOIC

The 74HC165D is an 8-bit parallel input/serial output shift register that features complementary serial outputs in a 16-pin SOIC package. This high-speed Si-gate CMOS device is JEDEC JEDSD 7A compliant. The 74HC165D offers Low Power Schottky TTL (LSTTL) pin compatibility. When the parallel load input is low, the parallel data from inputs D0 to D7 is loaded into the register asynchronously. When the parallel load input is high, data enters the serial register on the DS input and shifts one place to the right with each positive clock transition. This function allows parallel to series converter expansion by connecting the Q7 output to the successive stage DS input. The clock input has an OR gate structure that allows one input to be used as an active-low clock enable input. The low-to-high state transition of the clock enable input should only occur while the clock input is high for predictable operation. Supply voltage range from 2V to 6V Synchronous serial input 8-bit parallel asynchronous loading It has ESD protection Ambient temperature range from -40°C to 125°C